RISC-V hviprio1h CSR Register

Address 0x656Privilege HypervisorAccess HRW / 32-bit RV32 high halfHypervisor and virtualization CSRs

hviprio1h is a upper 32 bits of hviprio1.

Related Search Terms

hviprio1h CSR hviprio1h 0x656 RISC-V AIA hviprio1 upper half interrupt priority

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

Reserved63:32HVIPRIO1_HIGH31:0RW

Field Map

Understand hviprio1h By Bit Fields

1 key fields

31:0

HVIPRIO1_HIGH

hviprio1h fields for hviprio1 upper half; detailed encoding follows the AIA specification.

HVIPRIO1_HIGH (bits 31:0) — hviprio1h fields for hviprio1 upper half; detailed encoding follows the AIA specification.

What This Field Controls

- hviprio1h fields for hviprio1 upper half; detailed encoding follows the AIA specification.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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Official Basis & Search Notes

hviprio1h is an AIA virtual-interrupt CSR. It is HS/M-side hypervisor state, not a VS supervisor CSR copy; guest access is governed by the H extension and relevant state-enable, AIA, Sstc, or Smcsrind rules.

hviprio1h address, access class, and width are checked against the official CSR tables: 0x656, HRW, 32-bit RV32 high half.

AIA defines hypervisor virtual-interrupt CSRs that augment hvip for injecting interrupts into VS level.

Exact fields and priority encoding are interpreted by the AIA VS-level interrupt rules.

When writing, modify only officially defined fields; handle WARL, WLRL, WPRI, and reserved fields according to the official specification and implementation behavior.

RISC-V Privileged Architecture Manual - CSR table RISC-V Advanced Interrupt Architecture CSR chapter RISC-V AIA VS-level interrupts

What To Check First When Reading This CSR

- hviprio1h is a Hypervisor-level CSR; its separate address is in the official HRW access class.
- Guest/VS software does not reach this H-level CSR through a supervisor CSR alias; access is controlled by the H extension and relevant optional-extension rules.

Risk Checks Before Writing

- When writing hviprio1h, modify only officially defined target fields and preserve WPRI, reserved, and unchanged fields.

Put It Back Into A Real Flow

Confirm the current software is in an M/HS context that may access Hypervisor CSRs.

Confirm that the H, AIA, Sstc, Smstateen, Smcsrind, or other defining extension is implemented.

Read or write only official fields; whether guest-related access succeeds or traps is controlled by the corresponding extension rules and state-enable state.

FAQ

Can hviprio1h be accessed through a supervisor CSR alias?

Do not treat hviprio1h as a VS CSR copy. It is an H-level CSR; whether guest/VS access to related functionality traps is defined by the H extension and the relevant optional extension.

Can state-enable CSRs control access to hviprio1h?

When Smstateen and AIA are implemented, AIA, IMSIC, or CSRIND bits in mstateen0/hstateen0 may control lower-privilege or VM access to related AIA state.