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CSR Bit Fields

RISC-V hviprio1h CSR Register

Address 0x656Privilege Hypervisor (H extension)Access HRW / 32-bit, RV32 only; bits 63:32 of its low-half CSRHypervisor and virtualization CSRs

hviprio1h is the RV32 alias for hviprio1 bits 63:32.

Related Search Terms
hviprio1h CSRhviprio1h 0x656RISC-V AIAhviprio1h RV32 high half
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
IPRIO1531:24WARL or read-only zeroIPRIO1423:16WARL or read-only zeroIPRIO1315:8WARL or read-only zeroIPRIO8_RESERVED7:0Read-only zero
Field Map

Understand hviprio1h By Bit Fields

4 key fields
7:0

IPRIO8_RESERVED

Read-only zero

Reserved for interrupt 8 priority; reads as zero.

IPRIO8_RESERVED (bits 7:0) — Reserved for interrupt 8 priority; reads as zero.

What This Field Controls

  • - Reserved for interrupt 8 priority; reads as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
15:8

IPRIO13

WARL or read-only zero

Unsigned priority number for counter-overflow interrupt 13.

IPRIO13 (bits 15:8) — Unsigned priority number for counter-overflow interrupt 13.

What This Field Controls

  • - Unsigned priority number for counter-overflow interrupt 13.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
23:16

IPRIO14

WARL or read-only zero

Unsigned priority number for interrupt 14.

IPRIO14 (bits 23:16) — Unsigned priority number for interrupt 14.

What This Field Controls

  • - Unsigned priority number for interrupt 14.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
31:24

IPRIO15

WARL or read-only zero

Unsigned priority number for interrupt 15.

IPRIO15 (bits 31:24) — Unsigned priority number for interrupt 15.

What This Field Controls

  • - Unsigned priority number for interrupt 15.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

hviprio1h is an AIA hypervisor CSR; it is not a VS CSR alias.

AIA VS-level interrupt rules define field layout, writability, and read-only-zero conditions.
This CSR aliases bits 63:32 of its low-half CSR.
RISC-V Advanced Interrupt Architecture v1.0 - VS-level interrupts

What To Check First When Reading This CSR

  • - This CSR exists only with the H extension and AIA; AIA mstateen0.AIA does not restrict M-mode access.
  • - This high-half CSR is available only when XLEN=32; accessing a high-half CSR when XLEN>32 is illegal.

Risk Checks Before Writing

  • - Write only defined, implemented writable fields; confirm a WARL field by reading it back.

Put It Back Into A Real Flow

1

Confirm that H and AIA are implemented.

2

Confirm RV32/RV64 and whether each field is read-only zero or implemented writable.