RISC-V mieh CSR Register

Address 0x314Privilege MachineAccess RW / 32-bit (RV32 only, high-half)Machine status, trap, and interrupt CSRs

With AIA implemented, mieh is the RV32 high 32-bit interrupt-enable CSR for mie, used to access enable bits for higher-numbered interrupts.

Related Search Terms

mieh CSR mieh 0x314 RV32 mie high high interrupt enable machine interrupt enable RISC-V mieh

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

mie[63:32]31:0Platform-defined; RW/RO0

Field Map

Understand mieh By Bit Fields

1 key fields

31:0

mie[63:32]

Platform-defined; RW/RO0

RV32 high-half access to mie[63:32]. Each bit corresponds to interrupt identity 32 through 63, which are designated for platform use. A bit must be writable if its interrupt can ever become pending, otherwise it must be read-only zero; all bits are permitted to be read-only zero.

mie[63:32] (bits 31:0) — RV32 high-half access to mie[63:32]. Each bit corresponds to interrupt identity 32 through 63, which are designated for platform use. A bit must be writable if its interrupt can ever become pending, otherwise it must be read-only zero; all bits are permitted to be read-only zero.

What This Field Controls

- RV32 high-half access to mie[63:32]. Each bit corresponds to interrupt identity 32 through 63, which are designated for platform use. A bit must be writable if its interrupt can ever become pending, otherwise it must be read-only zero; all bits are permitted to be read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

AIA requires mieh on RV32 to access the high 32 bits of mie. It is not a pending CSR; high pending bits are represented by the corresponding miph.

The AIA CSR table defines mieh at 0x314 as the Machine RW high-half CSR and requires it on RV32 to access mie[63:32]; without AIA, this CSR must not be assumed to exist.

mieh bits 31:0 correspond to interrupt identities 63:32, which are designated for platform use; miph supplies the corresponding pending high half.

An enable bit must be writable if its interrupt can ever become pending, otherwise it is read-only zero. AIA explicitly permits every accessed mieh bit to be read-only zero.

RISC-V Privileged Architecture Manual - CSR Listing (2026-07-09)RISC-V Advanced Interrupt Architecture v1.0 - Added CSRs

What To Check First When Reading This CSR

- AIA requires mieh on RV32 as the 32-bit high-half CSR at 0x314 for mie[63:32]; this high-half CSR does not exist on RV64. Without AIA, mieh must not be assumed to exist.
- Bit n of mieh corresponds to interrupt identity n+32 and pairs with the pending state in the same bit of miph.
- AIA permits all accessed bits of mieh to be read-only zero; reading zero does not prove that a corresponding enableable interrupt exists.

Risk Checks Before Writing

- Modify only interrupt-enable bits defined by the platform and confirmed writable; other bits may be read-only zero.
- Use CSRRS/CSRRC to change target bits and read them back; do not treat the entire high half as unconditionally writable.

Put It Back Into A Real Flow

During initialization or the relevant privileged flow, software reads mieh to observe the current state.

Modify only the target fields while preserving all other bits.

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.

FAQ

What is the difference between mieh and miph?

On RV32, mieh is the high-half CSR for mie[63:32], while miph is the high-half CSR for mip[63:32]; the former accesses interrupt-enable bits and the latter accesses interrupt-pending bits.