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CSR Bit Fields

RISC-V miph CSR Register

Address 0x354Privilege MachineAccess MRW / RV32 high-half / 32-bitMachine AIA, timer, and indirect interrupt CSRs

AIA RV32 high-half CSR for the upper 32 bits of the widened mip interrupt-pending register.

Related Search Terms
miph CSRmiph 0x354RISC-V AIAmachine interruptRV32 high half
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Field Map

Understand miph By Bit Fields

0 key fields
Official Basis & Search Notes

AIA RV32 high-half CSR for the upper 32 bits of the widened mip interrupt-pending register.

The official AIA table lists miph at 0x354, with MRW access and RV32 high-half / 32-bit width.
miph is an RV32-only high-half CSR.
This page avoids older generic trap/debug wording.
RISC-V Advanced Interrupt Architecture: Added CSRs

What To Check First When Reading This CSR

  • - Check miph address, access class, and width against the official AIA CSR table.
  • - Do not assign fixed meaning to reserved bits or unimplemented interrupt bits.

Risk Checks Before Writing

  • - Modify only target fields and preserve reserved or undefined bits.
  • - Confirm that the hart implements AIA and that the relevant high-half interrupt-pending bits are not read-only zero before relying on this CSR.

Put It Back Into A Real Flow

1

Confirm that the hart implements AIA and that the current environment is RV32.

2

Read miph and interpret machine interrupt-pending bits according to the AIA definition of mip[63:32].

3

Use only the listed official fields as portable facts; handle other bits according to the implementation and specification.

FAQ

Is miph a standard AIA CSR?

Yes. This page follows the address, access class, and width in the official AIA CSR table.

Can unlisted miph bits be written freely?

No. Reserved, unimplemented, and implementation-defined bits must be handled according to the official specification and implementation requirements.