RISC-V miph CSR Register

Address 0x354Privilege MachineAccess MRW / RV32 high-half / 32-bitMachine AIA, timer, and indirect interrupt CSRs

AIA RV32 high-half CSR for the upper 32 bits of the widened mip interrupt-pending register.

Related Search Terms

miph CSR miph 0x354 RISC-V AIA machine interrupt RV32 high half

Bit Overview

Hover for details · Click to jump

bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

Reserved63:32MIPH31:0MRW

Field Map

Understand miph By Bit Fields

1 key fields

31:0

MIPH

MRW

miph fields as defined by AIA; detailed bit encoding follows the official AIA specification.

MIPH (bits 31:0) — miph fields as defined by AIA; detailed bit encoding follows the official AIA specification.

What This Field Controls

- miph fields as defined by AIA; detailed bit encoding follows the official AIA specification.

Common Values

miph high-half pending bits

0Not pending

Only for official AIA-defined RV32 mip[63:32] high-half machine interrupt-pending bits implemented as valid: 0 means the corresponding interrupt is not pending; reserved, undefined, or unimplemented bits do not have this fixed meaning.

1Pending

Only for official AIA-defined RV32 mip[63:32] high-half machine interrupt-pending bits implemented as valid: 1 means the corresponding interrupt is pending; delivery also depends on enable, global interrupt, delegation, virtualization, and interrupt-controller state.

Official Basis & Search Notes

AIA RV32 high-half CSR for the upper 32 bits of the widened mip interrupt-pending register.

The official AIA table lists miph at 0x354, with MRW access and RV32 high-half / 32-bit width.

miph is an RV32-only high-half CSR.

This page avoids older generic trap/debug wording.

RISC-V Advanced Interrupt Architecture: Added CSRs

What To Check First When Reading This CSR

- Check miph address, access class, and width against the official AIA CSR table.
- Do not assign fixed meaning to reserved bits or unimplemented interrupt bits.

Risk Checks Before Writing

- Modify only target fields and preserve reserved or undefined bits.
- Confirm AIA/IMSIC and the relevant supervisor-level support before relying on this CSR.

Put It Back Into A Real Flow

Confirm that the hart implements AIA and the relevant component such as S-mode or IMSIC.

Read miph and interpret it according to the AIA definition for virtual interrupts.

Use only the listed official fields as portable facts; handle other bits according to the implementation and specification.

FAQ

Is miph a standard AIA CSR?

Yes. This page follows the address, access class, and width in the official AIA CSR table.

Can unlisted miph bits be written freely?

No. Reserved, unimplemented, and implementation-defined bits must be handled according to the official specification and implementation requirements.