AIA machine top external interrupt CSR; exists only when an IMSIC is implemented.
AIA specifies that all other bits in a *topei return value are zeros.
Reserved (bits MXLEN-1:27) — AIA specifies that all other bits in a *topei return value are zeros.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
On read, reports the minor identity of the current highest-priority pending-and-enabled external interrupt in the IMSIC machine-level interrupt file; on write, the current readable identity is used to clear the corresponding pending bit.
Interrupt identity (bits 26:16) — On read, reports the minor identity of the current highest-priority pending-and-enabled external interrupt in the IMSIC machine-level interrupt file; on write, the current readable identity is used to clear the corresponding pending bit.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
AIA specifies that all other bits in a *topei return value are zeros.
Reserved (bits 15:11) — AIA specifies that all other bits in a *topei return value are zeros.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
On read, returns the external-interrupt priority encoding, the same as the interrupt identity; a zero return means no interrupt is currently reportable through mtopei.
Interrupt priority (bits 10:0) — On read, returns the external-interrupt priority encoding, the same as the interrupt identity; a zero return means no interrupt is currently reportable through mtopei.
A read of mtopei returning 0 means either no external interrupt is pending and enabled, or eithreshold is nonzero and no pending-and-enabled external interrupt has an identity below the threshold; writing while the value is zero has no effect.
AIA machine top external interrupt CSR; exists only when an IMSIC is implemented.
Confirm that the hart implements AIA and an IMSIC machine-level interrupt file.
Read mtopei and interpret it according to the AIA definition for top external interrupt.
Claim the currently reported external interrupt with a CSR instruction that reads and writes the CSR together; a write has no effect when mtopei is zero.
Yes. This page follows the address, access class, and width in the official AIA CSR table.
No. AIA specifies that the written value is ignored; the current readable interrupt identity determines the claim, and the other return bits are zeros.