RISC-V mtopei CSR Register

Address 0x35CPrivilege MachineAccess MRW / MXLENMachine AIA, timer, and indirect interrupt CSRs

AIA machine top external interrupt CSR; exists only when an IMSIC is implemented.

Related Search Terms

mtopei CSR mtopei 0x35C RISC-V AIA machine interrupt interrupt control

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

Reserved63:1MTOPEI0MRW

Field Map

Understand mtopei By Bit Fields

1 key fields

MXLEN-1:0

MTOPEI

MRW

mtopei fields as defined by AIA; detailed bit encoding follows the official AIA specification.

MTOPEI (bits MXLEN-1:0) — mtopei fields as defined by AIA; detailed bit encoding follows the official AIA specification.

What This Field Controls

- mtopei fields as defined by AIA; detailed bit encoding follows the official AIA specification.

Common Values

mtopei report value

0No reportable external interrupt

A read of mtopei returning 0 means there is no highest-priority machine external interrupt currently reportable and claimable through mtopei; nonzero values contain dynamic interrupt identity/priority information and should not be enumerated as fixed IDs.

Official Basis & Search Notes

AIA machine top external interrupt CSR; exists only when an IMSIC is implemented.

The official AIA table lists mtopei at 0x35C, with MRW access and MXLEN width.

mtopei exists only when an IMSIC is implemented.

This page avoids older generic trap/debug wording.

RISC-V Advanced Interrupt Architecture: Added CSRs

What To Check First When Reading This CSR

- Check mtopei address, access class, and width against the official AIA CSR table.
- mtopei exists only when an IMSIC is implemented; access cannot be assumed otherwise.

Risk Checks Before Writing

- Modify only target fields and preserve reserved or undefined bits.
- Confirm AIA/IMSIC and the relevant supervisor-level support before relying on this CSR.

Put It Back Into A Real Flow

Confirm that the hart implements AIA and the relevant component such as S-mode or IMSIC.

Read mtopei and interpret it according to the AIA definition for top external interrupt.

Use only the listed official fields as portable facts; handle other bits according to the implementation and specification.

FAQ

Is mtopei a standard AIA CSR?

Yes. This page follows the address, access class, and width in the official AIA CSR table.

Can unlisted mtopei bits be written freely?

No. Reserved, unimplemented, and implementation-defined bits must be handled according to the official specification and implementation requirements.