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CSR Bit Fields

RISC-V vstimecmph CSR Register

Address 0x25DPrivilege Hypervisor direct / VS aliasAccess HRW / 32-bit RV32 high half onlyHypervisor and virtualization CSRs

vstimecmph is an RV32-only CSR that accesses bits 63:32 of the 64-bit vstimecmp value. VS-mode reaches this state through the stimecmph alias, subject to Sstc, menvcfg.STCE, henvcfg.STCE, and mcounteren.TM/hcounteren.TM gating.

Related Search Terms
vstimecmph CSRvstimecmph 0x25Dvstimecmp high halfSstc vstimecmpRV32 high half
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
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Understand vstimecmph By Bit Fields

0 key fields
Official Basis & Search Notes

vstimecmph exists only for RV32 and accesses the upper 32 bits of the VS timer compare value. VS-mode access to stimecmph is substituted to the high half of vstimecmp, and it is available only when the relevant Sstc and counter-access gates allow it.

The CSR table gives vstimecmph address 0x25D, HRW access, and identifies it as the RV32-only upper 32 bits of vstimecmp.
vstimecmp is a 64-bit compare value; hip.VSTIP eventually becomes set when (time + htimedelta), truncated to 64 bits, is greater than or equal to vstimecmp.
VS-mode accesses vstimecmp through the stimecmp/stimecmph aliases; if Sstc is absent or menvcfg.STCE/henvcfg.STCE or mcounteren.TM/hcounteren.TM do not permit access, the access traps as specified.
RV64 has no vstimecmph high-half CSR; software accesses the 64-bit vstimecmp directly.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - Hypervisor extensionRISC-V Sstc extension

What To Check First When Reading This CSR

  • - vstimecmph's separate CSR address is in the official HRW access class; VS-mode reaches this VS timer-compare high half through the stimecmph supervisor CSR alias.
  • - Before reading it, confirm that H and Sstc are implemented and that menvcfg.STCE, henvcfg.STCE, mcounteren.TM, and hcounteren.TM allow the access.

Risk Checks Before Writing

  • - On RV32, writing vstimecmph updates only bits 63:32 of the 64-bit vstimecmp value; coordinate it with low-half vstimecmp writes to avoid a transient unintended timer compare.

Put It Back Into A Real Flow

1

Confirm that Sstc/H and relevant enable bits are implemented.

2

On RV32, handle it as the high-half CSR access path.

3

Do not confuse time offset with timer compare state.

FAQ

Is vstimecmph part of 64-bit timer state?

Yes. vstimecmph is the RV32-only high-half CSR for bits 63:32 of the 64-bit vstimecmp value.

How is vstimecmph related to time?

It participates in VS-level timer compare: when time+htimedelta reaches or exceeds vstimecmp, hip.VSTIP eventually becomes set and is delivered according to interrupt-enable and delegation rules while V=1.