Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VMAX.VX
RISC-V VMAX.VX Instruction Details
Instruction ManualR-typeSelect the larger value element by signed integer ordering and write the selected SEW-bit pattern to vd.
Instruction Syntax
vmax.vx vd, vs2, rs1, vm
Operand Breakdown
vd: mask destination register, with one Boolean result bit per element.
vs2/vs1 or scalar source: compared at the current SEW.
vm: vm=0 uses v0 to restrict participating elements, and vm=1 is unmasked.
VVector IntegerMin/Max
Instruction Behavior
VMAX.VX is the RISC-V V extension vector-scalar signed maximum instruction. Each active body element reads vs2[i] and integer scalar x[rs1], compares them by signed integer ordering, and writes the selected original SEW-bit pattern to vd; with vm=0, the v0 mask controls which elements execute.
VMAX.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VMAX compares active elements as signed integers and writes the larger SEW-bit pattern to vd.
Instruction input
vmax.vx
OP-V encodingvmax.vx
funct6
000111
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
max
max
max
max
max
max
max
max
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vmax.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer signed maximum, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VMAX.VX compares vs2 with x[rs1] after the XLEN/SEW scalar rule lane by lane for active elements within the current vl and selects the larger value by signed integer ordering. The result is the selected source element's SEW-bit pattern written to vd; it does not compute a difference or produce overflow or exception flags.
VMAX uses OP-V vector-arithmetic encoding with funct6=000111; the .vx form is selected by funct3=100.
The core semantic relation compares vs2[i] with the x[rs1] scalar after the XLEN/SEW truncation or sign-extension rule for active elements by signed integer ordering, then writes the larger value's original SEW-bit pattern to vd[i].
VMIN/VMAX use signed integer ordering; the sign bit is interpreted at SEW width for comparison, but the selected source element pattern is written back unchanged.
Only body elements within the current vl are processed; vm=0 uses the v0 mask and vm=1 is unmasked, while mask-off and tail destination elements follow the current vtype policies.
Vector Execution Context
When reading VMAX.VX, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vx: one vector source and one integer scalar source participate.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Data Clipping
Understand this scenario with real code like «vmax.vx v4, v8, a1, v0.t».
Thresholding
Understand this scenario with real code like «vmax.vx v4, v8, a1, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
VMAX selects one source element pattern; it is not addition, subtraction, or a saturating operation.
Signed forms interpret each SEW-wide source element as a two's-complement signed integer, so a value with the top bit set can be smaller than one with the top bit clear.
The VX form takes its second source from integer register x[rs1]; if XLEN>SEW the low SEW bits are used, and if XLEN<SEW the value is sign-extended to SEW before comparison.
With vm=0, masked-off body elements do not perform this compare; their destination elements follow the current mask policy and must not be assumed to become zero.
FAQ
How does VMAX.VX differ from the unsigned form?
VMAX.VX uses signed integer ordering; the corresponding U form uses unsigned integer ordering. Both write back the selected source's SEW-bit pattern; the .vx scalar source first follows the XLEN/SEW scalar rule.
Does VMAX.VX produce overflow or exception flags?
No. VMAX.VX compares and selects a source element pattern; it does not perform add/subtract overflow computation and does not set integer or floating-point exception flags.
How do vm and v0.t affect VMAX.VX?
With vm=0, only body elements whose v0.t bit is 1 execute the compare; with vm=1, body elements within the current vl are active. Masked-off and tail destination elements follow the current vtype policies.