Select the larger value element by signed integer ordering and write the selected SEW-bit pattern to vd.
Extension condition: Requires V 1.0, enabled vector state, valid vtype, and supported element widths.
VMAX.VX is the RISC-V V extension vector-scalar signed maximum instruction. Each active body element reads vs2[i] and integer scalar x[rs1], compares them by signed integer ordering, and writes the selected original SEW-bit pattern to vd; with vm=0, the v0 mask controls which elements execute.
Starts from OP-V encoding fields, then shows how VMAX compares active elements as signed integers and writes the larger SEW-bit pattern to vd.
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
vmax.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer signed maximum, mask control, and vd writeback. It does not model pipelines, caches, or timing.
VMAX.VX compares vs2 with x[rs1] after the XLEN/SEW scalar rule lane by lane for active elements within the current vl and selects the larger value by signed integer ordering. The result is the selected source element's SEW-bit pattern written to vd; it does not compute a difference.
vd is the SEW-bit destination; compare vs2 and the second source by two’s-complement signed ordering and select the larger source pattern.
rs1 selects an integer x-register: take low SEW bits when XLEN>SEW, sign-extend when XLEN<SEW; x0 supplies zero.
Require V 1.0, enabled vector state, valid vtype, and supported widths. Same-EEW source/destination overlap is allowed; masked vd cannot cover v0, and v0 cannot supply both EEW=1 mask and SEW data.
Body is vstart≤i<vl; omitting v0.t means vm=1 and including it means vm=0. Prestart is unchanged; inactive/tail follow vma/vta, with no guarantee of zero agnostic values. VL=0 or vstart≥vl updates no destination.
Assume RV32/RV64 V, enabled vector state, supported e32,m1, and VLEN≥128; after vsetivli, vl=4, vstart=0, ta/ma, with initialized sources and v0.mask=[1,0,1,1]. v8=[0xffffffff,2,0x80000000,7], x11=3 → v4=[3,policy,3,7]. policy means mask-agnostic: retain the old value or write all ones; tails are likewise not guaranteed zero.
VMAX.VX uses signed integer ordering; the corresponding U form uses unsigned integer ordering. Both write back the selected source's SEW-bit pattern; the .vx scalar source first follows the XLEN/SEW scalar rule.
vm=0 uses v0.t and enables only elements where vstart≤i<vl and the mask bit is 1. vm=1 is unmasked. Prestart is unchanged; inactive/tail elements follow vma/vta. With VL=0 or vstart≥vl, even tails are unchanged.