RISC-V Register Table: x0-x31, ABI Names, and Calling Convention

Return address register; JAL stores return address here, RET pseudo-instruction returns via this register. x1 is the standard link register.

Stack pointer register, points to the top of the stack (stack grows downward). Standard calling convention uses x2 as stack pointer.

Machine-mode status register containing global interrupt enables, privilege-level stack, and extension state control fields.

Supervisor address translation and protection register; controls the virtual memory paging scheme for S-mode.

Machine trap-vector base-address register; holds the entry address of the M-mode trap handler.

Machine exception program counter; holds the address of the instruction that triggered a trap.

Machine trap cause register; records the event type and cause code that triggered a trap.

Supervisor status register; a restricted view of mstatus containing S-mode-relevant fields.

Machine interrupt-enable register; controls which interrupts can be taken in M-mode.

pc is the program counter holding the current instruction address; branches, jumps, traps, and trap returns update it implicitly.

Machine interrupt-pending register; indicates which interrupts are currently pending.

Callee-saved register 0 / frame pointer. The psABI says that if a frame pointer exists, it must reside in x8 (s0/fp); it must be preserved across calls.

Callee-saved register 1; must be preserved across function calls.

Function argument register 0 / Return value register 0. Passes first argument and receives function return value. Not preserved across calls.

Function argument register 1 / return-value register 1. Passes the second argument and may be used with a0 for values returned in two argument registers.

Function argument register 2. Passes third argument.

Function argument register 3. Passes fourth argument.

Function argument register 4. Passes fifth argument.

Function argument register 5. Passes sixth argument.

Function argument register 6. Passes seventh argument.

Function argument register 7. The psABI uses it for the eighth integer argument.

Callee-saved register 2; must be preserved across function calls.

Callee-saved register 3; must be preserved across function calls.

Callee-saved register 4; must be preserved across function calls.

Callee-saved register 5; must be preserved across function calls.

Callee-saved register 6; must be preserved across function calls.

Callee-saved register 7; must be preserved across function calls.

Callee-saved register 8; must be preserved across function calls.

Callee-saved register 9; must be preserved across function calls.

Callee-saved register 10; must be preserved across function calls.

Callee-saved register 11; must be preserved across function calls.

Machine trap value register; holds additional information related to the trap.

Temporary register 0 (x5), also noted by the RISC-V ISA as an alternate link register. The psABI classifies t0 as a temporary register, so its value is not preserved across calls.

Temporary register 1 (x6). The psABI classifies t1 as a temporary register for short-lived intermediate values; its value is not preserved across calls.

Temporary register 2 (x7). The psABI classifies t2 as a temporary register for short-lived intermediate values; its value is not preserved across calls.

Temporary register 3 (x28). The psABI classifies t3 as a temporary register for caller-managed short-lived values; its value is not preserved across calls.

Temporary register 4 (x29). The psABI classifies t4 as a temporary register for caller-managed short-lived values; its value is not preserved across calls.

Temporary register 5 (x30). The psABI classifies t5 as a temporary register for caller-managed short-lived values; its value is not preserved across calls.

Temporary register 6 (x31). The psABI classifies t6 as a temporary register for caller-managed short-lived values; its value is not preserved across calls.

vl at 0xC20 is a Vector length CSR: holds the number of vector elements processed by current RVV instructions.

vtype at 0xC21 is a Vector type CSR: describes vector element width, LMUL, tail policy, and mask policy.

vlenb at 0xC22 is a Vector register length bytes CSR: read-only byte length of one architectural vector register.

Supervisor trap-vector base-address register; holds S-mode trap handler entry address.

Supervisor exception program counter; holds the address of the instruction that triggered an S-mode trap.

Supervisor trap cause register; records the event type and cause code that triggered an S-mode trap.

cycle is a user-level cycle counter CSR for the count visible through RDCYCLE.

time is a user-level timer CSR for the value visible through RDTIME.

instret is a user-level instructions-retired counter CSR for the count visible through RDINSTRET.

Global pointer register. The psABI marks gp unallocatable, so normal procedures should not modify it.

Thread pointer register, points to the thread-local storage (TLS) area of the current thread.

Floating-point control and status register; combines frm (rounding mode) and fflags (exception flags).

Supervisor interrupt-enable register; a view of mie bits relevant to S-mode.

Supervisor interrupt-pending register; a view of mip bits relevant to S-mode.

Floating-point exception flags register; accrues IEEE-754 exceptions from FP operations.

Floating-point dynamic rounding mode register; specifies the rounding mode for FP operations.

Supervisor counter-enable register; controls whether U-mode can access hardware counters.

Supervisor environment configuration register; controls execution-environment features in S-mode.

Supervisor scratch register; freely available for use by S-mode trap handlers.

Supervisor trap value register; holds additional information for S-mode traps.

Machine ISA register reporting ISA extensions supported by the current hart.

Machine exception delegation register; controls which exceptions are delegated to S-mode.

Machine interrupt delegation register; controls which interrupts are delegated to S-mode.

Machine counter-enable register; controls whether lower privilege levels can access hardware counters.

Machine environment configuration register; controls execution-environment features in machine mode.

Additional machine status register (RV32 only); holds extra fields of mstatus that don't fit in 32 bits.

Machine scratch register; freely available for use by M-mode trap handlers.

Machine trap instruction transformed register (H extension only); holds the transformed trap instruction.

Machine second trap value register (H extension only); holds guest physical address for two-stage translation faults.

Machine cycle counter; RW in M-mode, counts clock cycles since the hart started running.

Machine instructions-retired counter; counts the number of instructions completed by the hart.

Machine hart ID; returns the unique identifier of the current hart.

fcsr is a floating-point control/status entry associated with rounding mode and accrued exception flags.

fflags is the floating-point accrued exception flags register, recording NV, DZ, OF, UF, NX exception flags from FP operations.

frm is the floating-point dynamic rounding mode register, setting rounding direction for FP operations (RNE/RTZ/RDN/RUP/RMM).

vcsr is the Vector Control/Status register (CSR 0x00F), providing unified single-CSR access to the vxrm (fixed-point rounding mode) and vxsat (fixed-point saturation flag) fields.

vl is the Vector Length register, holding the number of elements to be processed by the current vector instruction, set by vsetvl/vsetvli or updated by fault-only-first loads.

vlenb is the Vector Register Byte Length register (read-only CSR 0xC22), holding VLEN/8 — the byte width of a single vector register.

vtype is the Vector Type register, encoding SEW (selected element width), LMUL (register group multiplier), and VTA/VMA (tail-agnostic / mask-agnostic) policies.

vxrm is the Vector Fixed-Point Rounding Mode register; a 2-bit field controlling the rounding mode (rne/rtz/rdn/rup/rmm) for fixed-point vector instructions.

vxsat is the Vector Fixed-Point Saturate Flag register; a single sticky bit set whenever a fixed-point vector instruction saturates its output. Cleared by vsetvl.

f8/fs0 is a floating-point register used by F/D/Q/Zfh instructions for operands, results, or FP call arguments.

f9/fs1 is a floating-point register used by F/D/Q/Zfh instructions for operands, results, or FP call arguments.

f10/fa0 is a floating-point register used by F/D/Q/Zfh instructions for operands, results, or FP call arguments.

f11/fa1 is a floating-point register used by F/D/Q/Zfh instructions for operands, results, or FP call arguments.

f12/fa2 is a floating-point register used by F/D/Q/Zfh instructions for operands, results, or FP call arguments.

f13/fa3 is a floating-point register used by F/D/Q/Zfh instructions for operands, results, or FP call arguments.

f14/fa4 is a floating-point register used by F/D/Q/Zfh instructions for operands, results, or FP call arguments.

f15/fa5 is a floating-point register used by F/D/Q/Zfh instructions for operands, results, or FP call arguments.

f16/fa6 is a floating-point register used by F/D/Q/Zfh instructions for operands, results, or FP call arguments.

f17/fa7 is a floating-point register used by F/D/Q/Zfh instructions for operands, results, or FP call arguments.

f18/fs2 is a floating-point register used by F/D/Q/Zfh instructions for operands, results, or FP call arguments.

f19/fs3 is a floating-point register used by F/D/Q/Zfh instructions for operands, results, or FP call arguments.

f20/fs4 is a floating-point register used by F/D/Q/Zfh instructions for operands, results, or FP call arguments.

f21/fs5 is a floating-point register used by F/D/Q/Zfh instructions for operands, results, or FP call arguments.

f22/fs6 is a floating-point register used by F/D/Q/Zfh instructions for operands, results, or FP call arguments.

f23/fs7 is a floating-point register used by F/D/Q/Zfh instructions for operands, results, or FP call arguments.

f24/fs8 is a floating-point register used by F/D/Q/Zfh instructions for operands, results, or FP call arguments.

f25/fs9 is a floating-point register used by F/D/Q/Zfh instructions for operands, results, or FP call arguments.

f26/fs10 is a floating-point register used by F/D/Q/Zfh instructions for operands, results, or FP call arguments.

f27/fs11 is a floating-point register used by F/D/Q/Zfh instructions for operands, results, or FP call arguments.

vstart records the element index from which a vector instruction resumes; software normally restores it to 0 after exception handling.

ssp at 0x011 is a Zicfiss shadow stack CSR: is a standard named CSR in the Zicfiss shadow stack category.

seed at 0x015 is a Scalar Crypto entropy CSR: is a standard named CSR in the Scalar Crypto entropy category.

stvt at 0x107 is retained as a compatibility/draft-origin CSR; the current official RISC-V Privileged and AIA CSR tables do not list it.

sstateen0 is a supervisor state-enable CSR controlling access to selected extension state from lower-privilege contexts.

sstateen1 is a supervisor state-enable CSR controlling access to selected extension state from lower-privilege contexts.

sstateen2 is a supervisor state-enable CSR controlling access to selected extension state from lower-privilege contexts.

sstateen3 is a supervisor state-enable CSR controlling access to selected extension state from lower-privilege contexts.

sieh (0x114) is the AIA RV32 high-half Supervisor interrupt-enable CSR for the upper 32 bits of sie.

scountinhibit (0x120) is defined by Smcdeleg/Ssccfg as a masked alias of the 32-bit mcountinhibit for S-mode access to inhibit bits of delegated counters.

snxti at 0x145 is retained as a compatibility/draft-origin CSR; the current official RISC-V Privileged and AIA CSR tables do not list it.

sintstatus at 0x146 is retained as a compatibility/draft-origin CSR; the current official RISC-V Privileged and AIA CSR tables do not list it.

sscratchcsw at 0x148 is retained as a compatibility/draft-origin CSR; the current official RISC-V Privileged and AIA CSR tables do not list it.

sscratchcswl at 0x149 is retained as a compatibility/draft-origin CSR; the current official RISC-V Privileged and AIA CSR tables do not list it.

stimecmp (0x14D) is the 64-bit Supervisor timer-compare CSR defined by Sstc; STIP becomes pending when time is greater than or equal to stimecmp.

sctrctl (0x14E) is the Supervisor Control Transfer Records control CSR, providing S-mode access to a subset of the 64-bit mctrctl; RV32 cannot access xctrctl[63:32].

sctrstatus (0x14F) is the 32-bit Supervisor CTR status CSR, holding CTR write-pointer and freeze state and updated by hardware when CTR is active.

siselect (0x150) is the Sscsrind Supervisor indirect-register select CSR that chooses which indirect register is accessed through sireg* aliases.

sireg (0x151) is an Sscsrind Supervisor indirect-register alias that accesses extension state selected by siselect.

sireg2 (0x152) is an Sscsrind Supervisor indirect-register alias 2 that accesses extension state selected by siselect.

sireg3 (0x153) is an Sscsrind Supervisor indirect-register alias 3 that accesses extension state selected by siselect.

siph (0x154) is the AIA RV32 high-half Supervisor interrupt-pending CSR for the upper 32 bits of sip.

sireg4 (0x155) is an Sscsrind Supervisor indirect-register alias 4 that accesses extension state selected by siselect.

sireg5 (0x156) is an Sscsrind Supervisor indirect-register alias 5 that accesses extension state selected by siselect.

sireg6 (0x157) is an Sscsrind Supervisor indirect-register alias 6 that accesses extension state selected by siselect.

stopei (0x15C) is the AIA/IMSIC Supervisor top external interrupt CSR, reporting and claiming the highest-priority pending-and-enabled external interrupt in the supervisor interrupt file.

stimecmph (0x15D) is the RV32 CSR for the upper 32 bits of the 64-bit stimecmp value.

sctrdepth (0x15F) is the 32-bit Supervisor CTR depth CSR; its WARL DEPTH field selects the CTR buffer depth.

srmcfg (0x181) is the Ssqosid Supervisor Resource Management Configuration CSR, using WARL RCID and MCID fields to configure resource-control and monitoring identifiers.

spmpen at 0x183 is a Supervisor PMP CSR: is a standard named CSR in the Supervisor PMP category.

spmpenh at 0x193 is a Control/status register CSR: is a standard named CSR in the RV32 high-half category.

scontext at 0x5A8 is a supervisor-mode context CSR listed under the official Debug/Trace Registers group.

scountovf at 0xDA0 is a supervisor read-only CSR reporting counter overflow state.

mtvt (0x307) is not listed in the current official RISC-V privileged/AIA CSR tables; this page keeps only a compatibility index and provides no portable access class, width, or bit-field definition.

AIA machine virtual interrupt-enable CSR for filtering and controlling supervisor-level virtual interrupts.

AIA machine virtual interrupt-pending CSR for supervisor-level virtual interrupt state.

mstateen0 at 0x30C is a State-enable control CSR: is a standard named CSR in the Machine state enable category.

mstateen1 at 0x30D is a State-enable control CSR: is a standard named CSR in the Machine state enable category.

mstateen2 at 0x30E is a State-enable control CSR: is a standard named CSR in the Machine state enable category.

mstateen3 at 0x30F is a State-enable control CSR: is a standard named CSR in the Machine state enable category.

medelegh is the RV32 high-half companion for machine exception delegation state.

midelegh is the RV32 high-half companion for machine interrupt delegation state.

mieh is an interrupt-enable CSR controlling which interrupts are enabled at the relevant privilege or virtualization level.

mpmpdeleg at 0x316 is a Control/status register CSR: is a standard named CSR in the PMP delegation category.

AIA RV32 high-half CSR for the upper 32 bits of mvien.

AIA RV32 high-half CSR for the upper 32 bits of mvip.

menvcfgh is the RV32 high-half companion for machine environment-configuration state.

mstateen0h at 0x31C is a State-enable control CSR: is a standard named CSR in the RV32 high-half mstateen category.

mstateen1h at 0x31D is a State-enable control CSR: is a standard named CSR in the RV32 high-half mstateen category.

mstateen2h at 0x31E is a State-enable control CSR: is a standard named CSR in the RV32 high-half mstateen category.

mstateen3h at 0x31F is a State-enable control CSR: is a standard named CSR in the RV32 high-half mstateen category.

mcountinhibit controls whether machine counters such as cycle and instret are allowed to increment.

mcyclecfg at 0x321 is the Smcntrpmf machine counter-configuration CSR that filters mcycle counting by privilege mode.

minstretcfg at 0x322 is the Smcntrpmf machine counter-configuration CSR that filters minstret counting by privilege mode.

mhpmevent3 at 0x323 is the machine HPM event-selector CSR for mhpmcounter3; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent4 at 0x324 is the machine HPM event-selector CSR for mhpmcounter4; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent5 at 0x325 is the machine HPM event-selector CSR for mhpmcounter5; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent6 at 0x326 is the machine HPM event-selector CSR for mhpmcounter6; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent7 at 0x327 is the machine HPM event-selector CSR for mhpmcounter7; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent8 at 0x328 is the machine HPM event-selector CSR for mhpmcounter8; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent9 at 0x329 is the machine HPM event-selector CSR for mhpmcounter9; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent10 at 0x32A is the machine HPM event-selector CSR for mhpmcounter10; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent11 at 0x32B is the machine HPM event-selector CSR for mhpmcounter11; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent12 at 0x32C is the machine HPM event-selector CSR for mhpmcounter12; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent13 at 0x32D is the machine HPM event-selector CSR for mhpmcounter13; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent14 at 0x32E is the machine HPM event-selector CSR for mhpmcounter14; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent15 at 0x32F is the machine HPM event-selector CSR for mhpmcounter15; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent16 at 0x330 is the machine HPM event-selector CSR for mhpmcounter16; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent17 at 0x331 is the machine HPM event-selector CSR for mhpmcounter17; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent18 at 0x332 is the machine HPM event-selector CSR for mhpmcounter18; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent19 at 0x333 is the machine HPM event-selector CSR for mhpmcounter19; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent20 at 0x334 is the machine HPM event-selector CSR for mhpmcounter20; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent21 at 0x335 is the machine HPM event-selector CSR for mhpmcounter21; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent22 at 0x336 is the machine HPM event-selector CSR for mhpmcounter22; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent23 at 0x337 is the machine HPM event-selector CSR for mhpmcounter23; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent24 at 0x338 is the machine HPM event-selector CSR for mhpmcounter24; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent25 at 0x339 is the machine HPM event-selector CSR for mhpmcounter25; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent26 at 0x33A is the machine HPM event-selector CSR for mhpmcounter26; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent27 at 0x33B is the machine HPM event-selector CSR for mhpmcounter27; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent28 at 0x33C is the machine HPM event-selector CSR for mhpmcounter28; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent29 at 0x33D is the machine HPM event-selector CSR for mhpmcounter29; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent30 at 0x33E is the machine HPM event-selector CSR for mhpmcounter30; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mhpmevent31 at 0x33F is the machine HPM event-selector CSR for mhpmcounter31; Sscofpmf also defines overflow and privilege-mode filtering fields in its upper bits.

mnxti (0x345) is not listed in the current official RISC-V privileged/AIA CSR tables; this page keeps only a compatibility index and provides no portable access class, width, or bit-field definition.

mintstatus (0x346) is not listed in the current official RISC-V privileged/AIA CSR tables; this page keeps only a compatibility index and provides no portable access class, width, or bit-field definition.

mscratchcsw (0x348) is not listed in the current official RISC-V privileged/AIA CSR tables; this page keeps only a compatibility index and provides no portable access class, width, or bit-field definition.

mscratchcswl (0x349) is not listed in the current official RISC-V privileged/AIA CSR tables; this page keeps only a compatibility index and provides no portable access class, width, or bit-field definition.

mctrctl is the machine-level control CSR for Smctr Control Transfer Records.

Smcsrind machine indirect register select CSR; selects the target reached by subsequent mireg* accesses.

Smcsrind machine indirect register alias CSR; accesses are redirected according to the current miselect value.

Smcsrind machine indirect register alias CSR; accesses are redirected according to the current miselect value.

Smcsrind machine indirect register alias CSR; accesses are redirected according to the current miselect value.

AIA RV32 high-half CSR for the upper 32 bits of the widened mip interrupt-pending register.

Smcsrind machine indirect register alias CSR; accesses are redirected according to the current miselect value.

Smcsrind machine indirect register alias CSR; accesses are redirected according to the current miselect value.

Smcsrind machine indirect register alias CSR; accesses are redirected according to the current miselect value.

AIA machine top external interrupt CSR; exists only when an IMSIC is implemented.

pmpcfg0 is a physical memory protection configuration CSR describing permissions, address matching, and lock bits for PMP regions.

pmpcfg1 is an RV32-only physical memory protection configuration CSR; odd-numbered pmpcfg CSRs are illegal on RV64.

pmpcfg2 is a physical memory protection configuration CSR describing permissions, address matching, and lock bits for PMP regions.

pmpcfg3 is an RV32-only physical memory protection configuration CSR; odd-numbered pmpcfg CSRs are illegal on RV64.

pmpcfg4 is a physical memory protection configuration CSR describing permissions, address matching, and lock bits for PMP regions.

pmpcfg5 is an RV32-only physical memory protection configuration CSR; odd-numbered pmpcfg CSRs are illegal on RV64.

pmpcfg6 is a physical memory protection configuration CSR describing permissions, address matching, and lock bits for PMP regions.

pmpcfg7 is an RV32-only physical memory protection configuration CSR; odd-numbered pmpcfg CSRs are illegal on RV64.

pmpcfg8 is a physical memory protection configuration CSR describing permissions, address matching, and lock bits for PMP regions.

pmpcfg9 is an RV32-only physical memory protection configuration CSR; odd-numbered pmpcfg CSRs are illegal on RV64.

pmpcfg10 is a physical memory protection configuration CSR describing permissions, address matching, and lock bits for PMP regions.

pmpcfg11 is an RV32-only physical memory protection configuration CSR; odd-numbered pmpcfg CSRs are illegal on RV64.

pmpcfg12 is a physical memory protection configuration CSR describing permissions, address matching, and lock bits for PMP regions.

pmpcfg13 is an RV32-only physical memory protection configuration CSR; odd-numbered pmpcfg CSRs are illegal on RV64.

pmpcfg14 is a physical memory protection configuration CSR describing permissions, address matching, and lock bits for PMP regions.

pmpcfg15 is an RV32-only physical memory protection configuration CSR; odd-numbered pmpcfg CSRs are illegal on RV64.

pmpaddr0 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr1 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr2 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr3 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr4 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr5 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr6 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr7 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr8 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr9 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr10 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr11 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr12 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr13 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr14 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr15 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr16 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr17 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr18 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr19 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr20 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr21 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr22 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr23 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr24 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr25 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr26 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr27 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr28 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr29 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr30 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr31 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr32 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr33 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr34 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr35 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr36 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr37 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr38 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr39 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr40 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr41 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr42 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr43 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr44 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr45 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr46 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr47 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr48 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr49 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr50 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr51 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr52 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr53 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr54 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr55 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr56 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr57 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr58 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr59 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr60 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr61 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr62 is a PMP address CSR holding address-matching information for a physical memory protection entry.

pmpaddr63 is a PMP address CSR holding address-matching information for a physical memory protection entry.

mcyclecfgh at 0x721 is the RV32 machine high-half CSR for bits 63:32 of mcyclecfg.

minstretcfgh at 0x722 is the RV32 machine high-half CSR for bits 63:32 of minstretcfg.

mhpmevent3h at 0x723 is the RV32 high-half CSR for bits 63:32 of mhpmevent3, provided with Sscofpmf.

mhpmevent4h at 0x724 is the RV32 high-half CSR for bits 63:32 of mhpmevent4, provided with Sscofpmf.

mhpmevent5h at 0x725 is the RV32 high-half CSR for bits 63:32 of mhpmevent5, provided with Sscofpmf.

mhpmevent6h at 0x726 is the RV32 high-half CSR for bits 63:32 of mhpmevent6, provided with Sscofpmf.

mhpmevent7h at 0x727 is the RV32 high-half CSR for bits 63:32 of mhpmevent7, provided with Sscofpmf.

mhpmevent8h at 0x728 is the RV32 high-half CSR for bits 63:32 of mhpmevent8, provided with Sscofpmf.

mhpmevent9h at 0x729 is the RV32 high-half CSR for bits 63:32 of mhpmevent9, provided with Sscofpmf.

mhpmevent10h at 0x72A is the RV32 high-half CSR for bits 63:32 of mhpmevent10, provided with Sscofpmf.

mhpmevent11h at 0x72B is the RV32 high-half CSR for bits 63:32 of mhpmevent11, provided with Sscofpmf.

mhpmevent12h at 0x72C is the RV32 high-half CSR for bits 63:32 of mhpmevent12, provided with Sscofpmf.

mhpmevent13h at 0x72D is the RV32 high-half CSR for bits 63:32 of mhpmevent13, provided with Sscofpmf.

mhpmevent14h at 0x72E is the RV32 high-half CSR for bits 63:32 of mhpmevent14, provided with Sscofpmf.

mhpmevent15h at 0x72F is the RV32 high-half CSR for bits 63:32 of mhpmevent15, provided with Sscofpmf.

mhpmevent16h at 0x730 is the RV32 high-half CSR for bits 63:32 of mhpmevent16, provided with Sscofpmf.

mhpmevent17h at 0x731 is the RV32 high-half CSR for bits 63:32 of mhpmevent17, provided with Sscofpmf.

mhpmevent18h at 0x732 is the RV32 high-half CSR for bits 63:32 of mhpmevent18, provided with Sscofpmf.

mhpmevent19h at 0x733 is the RV32 high-half CSR for bits 63:32 of mhpmevent19, provided with Sscofpmf.

mhpmevent20h at 0x734 is the RV32 high-half CSR for bits 63:32 of mhpmevent20, provided with Sscofpmf.

mhpmevent21h at 0x735 is the RV32 high-half CSR for bits 63:32 of mhpmevent21, provided with Sscofpmf.

mhpmevent22h at 0x736 is the RV32 high-half CSR for bits 63:32 of mhpmevent22, provided with Sscofpmf.

mhpmevent23h at 0x737 is the RV32 high-half CSR for bits 63:32 of mhpmevent23, provided with Sscofpmf.

mhpmevent24h at 0x738 is the RV32 high-half CSR for bits 63:32 of mhpmevent24, provided with Sscofpmf.

mhpmevent25h at 0x739 is the RV32 high-half CSR for bits 63:32 of mhpmevent25, provided with Sscofpmf.

mhpmevent26h at 0x73A is the RV32 high-half CSR for bits 63:32 of mhpmevent26, provided with Sscofpmf.

mhpmevent27h at 0x73B is the RV32 high-half CSR for bits 63:32 of mhpmevent27, provided with Sscofpmf.

mhpmevent28h at 0x73C is the RV32 high-half CSR for bits 63:32 of mhpmevent28, provided with Sscofpmf.

mhpmevent29h at 0x73D is the RV32 high-half CSR for bits 63:32 of mhpmevent29, provided with Sscofpmf.

mhpmevent30h at 0x73E is the RV32 high-half CSR for bits 63:32 of mhpmevent30, provided with Sscofpmf.

mhpmevent31h at 0x73F is the RV32 high-half CSR for bits 63:32 of mhpmevent31, provided with Sscofpmf.

RNMI scratch register used by resumable non-maskable interrupt handlers to save and restore context.

RNMI exception program counter holding the interrupted PC on RNMI entry.

RNMI cause register recording the RNMI interrupt or double-trap exception cause code.

RNMI status register saving interrupted-context privilege, virtualization, and RNMI enable state.

mseccfg at 0x747 is a Machine security config CSR: is a standard named CSR in the Machine security config category.

mseccfgh at 0x757 is a Control/status register CSR: is a standard named CSR in the RV32 high-half category.

mcontext at 0x7A8 is a Debug context CSR: is a standard named CSR in the Debug context category.

mscontext at 0x7AA is a Debug context CSR: is a standard named CSR in the Debug context category.

mhpmcounter3 at 0xB03 is machine hardware performance-monitor counter 3, a 64-bit counter for the event selected by mhpmevent3.

mhpmcounter4 at 0xB04 is machine hardware performance-monitor counter 4, a 64-bit counter for the event selected by mhpmevent4.

mhpmcounter5 at 0xB05 is machine hardware performance-monitor counter 5, a 64-bit counter for the event selected by mhpmevent5.

mhpmcounter6 at 0xB06 is machine hardware performance-monitor counter 6, a 64-bit counter for the event selected by mhpmevent6.

mhpmcounter7 at 0xB07 is machine hardware performance-monitor counter 7, a 64-bit counter for the event selected by mhpmevent7.

mhpmcounter8 at 0xB08 is machine hardware performance-monitor counter 8, a 64-bit counter for the event selected by mhpmevent8.

mhpmcounter9 at 0xB09 is machine hardware performance-monitor counter 9, a 64-bit counter for the event selected by mhpmevent9.

mhpmcounter10 at 0xB0A is machine hardware performance-monitor counter 10, a 64-bit counter for the event selected by mhpmevent10.

mhpmcounter11 at 0xB0B is machine hardware performance-monitor counter 11, a 64-bit counter for the event selected by mhpmevent11.

mhpmcounter12 at 0xB0C is machine hardware performance-monitor counter 12, a 64-bit counter for the event selected by mhpmevent12.

mhpmcounter13 at 0xB0D is machine hardware performance-monitor counter 13, a 64-bit counter for the event selected by mhpmevent13.

mhpmcounter14 at 0xB0E is machine hardware performance-monitor counter 14, a 64-bit counter for the event selected by mhpmevent14.

mhpmcounter15 at 0xB0F is machine hardware performance-monitor counter 15, a 64-bit counter for the event selected by mhpmevent15.

mhpmcounter16 at 0xB10 is machine hardware performance-monitor counter 16, a 64-bit counter for the event selected by mhpmevent16.

mhpmcounter17 at 0xB11 is machine hardware performance-monitor counter 17, a 64-bit counter for the event selected by mhpmevent17.

mhpmcounter18 at 0xB12 is machine hardware performance-monitor counter 18, a 64-bit counter for the event selected by mhpmevent18.

mhpmcounter19 at 0xB13 is machine hardware performance-monitor counter 19, a 64-bit counter for the event selected by mhpmevent19.

mhpmcounter20 at 0xB14 is machine hardware performance-monitor counter 20, a 64-bit counter for the event selected by mhpmevent20.

mhpmcounter21 at 0xB15 is machine hardware performance-monitor counter 21, a 64-bit counter for the event selected by mhpmevent21.

mhpmcounter22 at 0xB16 is machine hardware performance-monitor counter 22, a 64-bit counter for the event selected by mhpmevent22.

mhpmcounter23 at 0xB17 is machine hardware performance-monitor counter 23, a 64-bit counter for the event selected by mhpmevent23.

mhpmcounter24 at 0xB18 is machine hardware performance-monitor counter 24, a 64-bit counter for the event selected by mhpmevent24.

mhpmcounter25 at 0xB19 is machine hardware performance-monitor counter 25, a 64-bit counter for the event selected by mhpmevent25.

mhpmcounter26 at 0xB1A is machine hardware performance-monitor counter 26, a 64-bit counter for the event selected by mhpmevent26.

mhpmcounter27 at 0xB1B is machine hardware performance-monitor counter 27, a 64-bit counter for the event selected by mhpmevent27.